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4M x 16-Bit Dynamic RAM (4k & 8k Refresh)
HYB 3164160T -50/-60 HYB 3165160T -50/-60
Preliminary Information
* * *
*
* *
* * * * * *
4 194 304 words by 16-bit organization 0 to 70 C operating temperature Fast access and cycle time RAS access time: 50 ns (-50 version) 60 ns (-60 version) Cycle time: 90 ns (-50 version) 110 ns (-60 version) CAS access time: 13 ns ( -50 version) 15 ns ( -60 version) Fast page mode cycle time 35 ns (-50 version) 40 ns (-60 version) Single + 3.3 V ( 0.3V) power supply Low power dissipation max. 396 active mW ( HYB 3164160T-50) max. 360 active mW ( HYB 3164160T-60) max. 504 active mW ( HYB 3165160T-50) max. 432 active mW ( HYB 3165160T-60) 7.2 mW standby (TTL) 720 W standby (MOS) Read, write, read-modify-write, CAS-before-RAS refresh (CBR), RAS-only refresh, hidden refresh and self refresh modes Fast page mode capability 2 CAS / 1 WRITE byte control 8192 refresh cycles/128 ms , 13 R/ 9C addresses (HYB 3164160T) 4096 refresh cycles/ 64 ms , 12 R/ 10C addresses (HYB 3165160T) Plastic Package: P-TSOPII-54-1 500 mil
Semiconductor Group
5
HYB 3164(5)160T-50/-60 4M x 16-DRAM
This device is a 64 MBit dynamic RAM organized 4 194 304 by 16 bits. The device is fabricated in SIEMENS/IBM most advanced first generation 64Mbit CMOS silicon gate process technology. The circuit and process design allow this device to achieve high performance and low power dissipation. This DRAM operates with a single 3.3 +/-0.3V power supply and interfaces with either LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB 3164(5)160T to be packaged in a 500 mil wide TSOP-54 plastic package. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. Ordering Information Type HYB 3164160T-50 HYB 3164160T-60 HYB 3165160T-50 HYB 3165160T-60 Pin Names A0-A12 A0-A11 RAS OE I/O1-I/O16 UCAS,LCAS WRITE Vcc Vss Address Inputs for HYB 3164160T Address Inputs for HYB 3165160T Row Address Strobe Output Enable Data Input/Output Column Address Strobe Read/Write Input Power Supply ( + 3.3V) Ground Ordering Code on request on request on request on request Package P-TSOPII-54-1 P-TSOPII-54-1 P-TSOPII-54-1 P-TSOPII-54-1 Descriptions 500 mil DRAM (access time 50 ns) 500 mil DRAM (access time 60 ns) 500 mil DRAM (access time 50 ns) 500 mil DRAM (access time 60 ns)
Semiconductor Group
6
HYB 3164(5)160T-50/-60 4M x 16-DRAM
P-SOJ-54-1 (500 mil) P-TSOPII-54-1 (500 mil)
* Pin 35 is A12 for HYB 3164160T and N.C. for HYB 3165160T Pin Configuration
Semiconductor Group
7
HYB 3164(5)160T-50/-60 4M x 16-DRAM
TRUTH TABLE
FUNCTION Standby Read:Word Read:Lower Byte Read:Upper Byte Write:Word (Early-Write) Write:Lower Byte (Early-Write) Write:Upper Byte (Early Write) Read-ModifyWrite Fast Page Mode Read (Word) Fast Page Mode Read (Word) 1st Cycle 2nd Cycle
RAS LCAS UCA S H L L L L L L L L L L L L L L H-X L L H L L H L H-L H-L H-L H-L H-L H-L H H-X H H L L H L L H-L H-L H-L H-L H-L H-L H L L L L
WRIT E X H H H L L L H-L H H L L H-L H-L X H L H L
OE X L L L X X X
ROW ADD X ROW ROW ROW ROW ROW ROW
COL ADD X COL COL COL COL COL COL COL COL COL COL COL COL COL n/a n/a n/a COL COL
I/O1I/O16
High Impedance Data Out Lower Byte:Data Out Upper-Byte:High-Z Lower Byte:High-Z Upper Byte:Data Out Data In Lower Byte:Data Out Upper-Byte:High-Z Lower Byte:High-Z Upper Byte:Data Out Data Out, Data In Data Out Data Out Data In Data In Data Out, Data In Data Out, Data In High Impedance High Impedance High Impedance Data Out Data In
L - H ROW L L X X ROW n/a ROW n/a
Fast Page Mode 1st Early Write(Word) Cycle Fast Page Mode 2nd Early Write(Word) Cycle Fast Page Mode RMW Fast Page Mode RMW RAS only refresh CAS-before-RAS refresh Test Mode Entry Hidden Refresh (Read) Hidden Refresh (Write) 1st Cycle 2st Cycle
L - H ROW L - H n/a X X X L X ROW X X ROW ROW
H-L L H-L L L-H- L L L-H- L L
Semiconductor Group
8
HYB 3164(5)160T-50/-60 4M x 16-DRAM
Block Diagram for HYB 3164160T
Semiconductor Group
9
HYB 3164(5)160T-50/-60 4M x 16-DRAM
Block Diagram for HYB 3165160T
Semiconductor Group
10
HYB 3164(5)160T-50/-60 4M x 16-DRAM
Absolute Maximum Ratings Operating temperature range..............................................................................................0 to 70 C Storage temperature range.........................................................................................- 55 to 150 C Input/output voltage..................................................................................-0.5 to min (Vcc+0.5,4.6) V Power supply voltage....................................................................................................-0.5V to 4.6 V Power dissipation......................................................................................................................1.0 W Data out current (short circuit)..................................................................................................50 mA Note
Stresses above those listed under Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may effect device reliability.
DC Characteristics TA = 0 to 70 C, VSS = 0 V, VCC = 3.3 V 0.3 V, (values in brackets for HYB 3165160T) Parameter Input high voltage Input low voltage Output high voltage (LVTTL) Output H" level voltage (Iout = -2mA) Output low voltage (LVTTL) Output L"level voltage (Iout = +2mA) Output high voltage (LVCMOS) Output H" level voltage (Iout = -100uA) Ouput low voltage (LVCMOS) Output L" level voltage (Iout = +100uA) Input leakage current,any input
(0 V < Vin < Vcc , all other pins = 0 V
Symbol
Limit Values min. max. Vcc+0.3 0.8 - 0.4 2.0 - 0.3 2.4 -
Unit Note V V V V V V A A 1) 1)
VIH VIL VOH VOL VOH VOL II(L) IO(L) ICC1
-50 ns version -60 ns version
Vcc-0.2 -2 -2 0.2 2 2
Output leakage current
(DO is disabled, 0 V < Vout < Vcc )
Average Vcc supply current:
- -
110 (140) mA 100 (120) mA 2 mA
2) 3) 4)
(RAS, CAS, address cycling: tRC = tRC min.)
Standby Vcc supply current
(RAS=CAS= Vih)
ICC2
-
-
Semiconductor Group
11
HYB 3164(5)160T-50/-60 4M x 16-DRAM
DC Characteristics (cont'd) TA = 0 to 70 C, VSS = 0 V, VCC = 3.3 V 0.3 V, (values in brackets for HYB 3165160T) Parameter Symbol Limit Values min. Average Vcc supply current, during RAS-only ICC3 refresh cycles: -50 ns version -60 ns version
(RAS cycling: CAS = VIH: tRC = tRC min.)
Unit Note
max. 110 (140) mA 100 (120) mA 2) 4)
- -
Average Vcc supply current,
during fast page mode: -50 ns version -60 ns version
ICC4
- -
85 (85) 75 (75) 200
mA mA A
2) 3) 4)
(RAS = VIL, CAS, address cycling: tPC=tPC min.)
Standby Vcc supply current
(RAS=CAS= Vcc-0.2V)
ICC5
-
-
Average Vcc supply current, during CAS-before- ICC6 RAS refresh mode: -50 ns version -60 ns version
(RAS, CAS cycling: tRC = tRC min.)
- - -
110 (140) mA 100 (120) mA 400 A
2) 4)
Self Refresh Current
Average Power Supply Current during Self Refresh. (CBR cycle with tRAS>TRASSmin, CAS held low, WE = Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)
ICC7
Capacitance TA = 0 to 70 C,VCC = 3.3 V 0.3V, f = 1 MHz Parameter Input capacitance (A0 to A11,A12) Input capacitance (RAS, CAS, WRITE, OE) I/O capacitance (I/O1-I/O16) Symbol Limit Values min. max. 5 7 7 pF pF pF - - - Unit
CI1 CI2 CIO
Semiconductor Group
12
HYB 3164(5)160T-50/-60 4M x 16-DRAM
AC Characteristics (note: 6,7,8) TA = 0 to 70 C,VCC = 3.3 0.3V Parameter Symbol HYB HYB Unit 3164(5)16T-50 3164(5)16T-60 min. max. - - 100k 100k - - - - 37 25 - - - 30 128 64 min. 110 40 60 15 0 10 0 10 20 15 15 60 5 3 - - max. - - 100k 100k - - - - 45 30 - - - 30 128 64 ns ns ns ns ns ms ms
7
Note
common parameters
Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period for HYB3164160T Refresh period for HYB3165160T tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH 90 30 50 13 0 8 0 10 18 13 13 50 5 3 - - ns ns ns ns ns ns ns ns
tCRP
tT tREF tREF
Read Cycle
Access time from RAS Access time from CAS Access time from column address OE access time Column address to RAS lead time Read command setup time Read command hold time Read command hold time referenced to RAS CAS to output in low-Z tRAC tCAC tAA tOEA tRAL tRCS tRCH tRRH tCLZ - - - - 25 0 0 0 0 50 13 25 13 - - - - - - - - - 30 0 0 0 0 60 15 30 15 - - - - - ns ns ns ns ns ns ns ns ns
11 11 8 8, 9 8, 9 8, 10 8
Semiconductor Group
13
HYB 3164(5)160T-50/-60 4M x 16-DRAM
AC Characteristics (cont'd)(note: 6,7,8) TA = 0 to 70 C,VCC = 3.3 0.3V Parameter Symbol HYB HYB Unit 3164(5)16T-50 3164(5)16T-60 min. Output buffer turn-off delay Output buffer turn-off delay from OE Data to OE low delay CAS high to data delay OE high to data delay tOFF tOEZ tDZO tCDD tODD - - 0 13 13 max. 13 13 - - - min. - - 0 15 15 max. 15 15 - - - ns ns ns ns ns
12 12 13 14 14
Note
Write Cycle
Write command hold time Write command pulse width Write command setup time Write command to RAS lead time Write command to CAS lead time Data setup time Data hold time CAS delay time from Din tWCH tWP tWCS tRWL tCWL tDS tDH tDZC 8 8 0 13 13 0 10 0 - - - - - - - - 10 10 0 15 15 0 10 0 - - - - - - - - ns ns ns ns ns ns ns ns
16 16 13 15
Read-Modify-Write Cycle
Read-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE command hold time tRWC tRWD tCWD tAWD tOEH 126 68 31 43 13 - - - - - 150 80 35 50 15 - - - - - ns ns ns ns ns
15 15 15
Fast Page Mode Cycle
Fast page mode cycle time CAS precharge time Access time from CAS precharge RAS pulse width CAS precharge to RAS Delay tPC tCP tCPA tRAS tRHCP 35 10 - 50 30 - - 30 200k - 40 10 - 60 35 - - 35 200k - ns ns ns ns ns
8
Semiconductor Group
14
HYB 3164(5)160T-50/-60 4M x 16-DRAM
AC Characteristics (cont'd)(note: 6,7,8) TA = 0 to 70 C,VCC = 3.3 0.3V Parameter Symbol HYB HYB Unit 3164(5)16T-50 3164(5)16T-60 min. max. min. max. Note
Fast Page Mode Read-Modify-Write Cycle
Fast page mode read-write cycle time CAS precharge to WE tPRWC tCPWD 71 48 - - 80 55 - - ns ns
CAS-before-RAS refresh cycle
CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time Write hold time referenced to RAS tCSR tCHR tRPC tWRP tWRH 5 10 5 10 10 - - - - - 5 10 5 10 10 - - - - - ns ns ns ns ns
CAS-before-RAS counter test cycle
CAS precharge time tCPT 25 - 30 - ns
Self Refresh Cycle
RAS pulse width RAS precharge time CAS hold time
tRASS
100k 90 -50
- - -
100k 110 -50
- - -
ns ns
17 17 17
tRPS tCHS
Semiconductor Group
15
HYB 3164(5)160T-50/-60 4M x 16-DRAM
Notes:
1) 2) 3) 4) All voltages are referenced to VSS. ICC1, ICC3, ICC4 and ICC6 and ICC7 depend on cycle rate. ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. Address can be changed once or less while RAS = Vil.In the case of ICC4 it can be changed once or less during a fast page mode cycle ( tpc). 5) An initial pause of 100 s is required after power-up followed by 8 RAS-only-refresh cycles, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 5 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 8) Measured with the specified current load and 100 pF at Voh = 2.0 V and Vol = 0.8 V. 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11) Either tRCH or tRRH must be satisfied for a read cycle. 12) tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 13) Either tDZC or tDZO must be satisfied. 14) Either tCDD or tODD must be satisfied. 15) tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate. 16) These parameters are referenced to CAS leading edge in early write cycles and to WRITE leading edge in Read-Modify-Write cycles. 17) When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refresh in an evenly distributed manner over the refresh iterval using CBR refresh cycles, then only one CBR cycle must be performed immediatly after exit from Self Refresh. If row addresses are being refresh in any other manner (ROR - Distributed/Burst or CBR-Burst) over the refresh interval, then a full set of row refreshed must be performed immediately before entry to and immediatey after exit from Self Refresh
Semiconductor Group
16
HYB 3164(5)160T-50/-60 4M x 16-DRAM
tRC tRAS
RAS
V IH VIL
tRP
tCSH tRCD tRSH tCAS tRAL tCAH
Column Address
tCRP
UCAS LCAS
V IH VIL
tRAD tASR tASC
tASR
Row Address
Address
V IH VIL
Row Address
tRCH tRAH tRCS tRRH tAA tOEA
WRITE
V IH VIL
OE
V IH VIL
tDZC tDZO tCAC tODD
tCDD
I/O1-I/O16 IH (Inputs) V
IL
V
tOFF tCLZ
Hi Z
tOEZ
Valid Data Out Hi Z
V I/O1-I/O16 OH
(Outputs) V
OL
tRAC
"H" or "L"
Read Cycle
Semiconductor Group
17
HYB 3164(5)160T-50/-60 4M x 16-DRAM
tRC tRAS
RAS
V IH VIL
tRP
tCSH tRCD tRSH tCAS tRAL tCAH
Column Address
tCRP
UCAS LCAS
V IH VIL
tRAD tASR tASC
tASR
Row Address
Address
V IH VIL
.
Row Address
tRAH
WRITE
V IH VIL
tCWL tWCS t WP tWCH tRWL
OE
V IH VIL
tDS
I/O1-I/O16 IH (Inputs) V
IL V
tDH
Valid Data In
I/O1-I/O16 OH (Outputs) V
OL
V
Hi Z
"H" or "L"
Write Cycle (Early Write)
Semiconductor Group
18
HYB 3164(5)160T-50/-60 4M x 16-DRAM
tRC tRAS
RAS
V IH VIL
tRP
tCSH tRCD tRSH tCAS tRAL
tCRP
UCAS LCAS
V IH VIL
tRAD tASR tASC tCAH
Column Address
tASR
Row Address
V IH
.
Address V IL
Row Address
tRAH
WRITE
V IH VIL
tCWL tRWL tWP
tOEH
OE
V IH VIL
tODD tDZO tDZC tDS tOEZ
tDH
V I/O1-I/O16 IH
(Inputs)
VIL
Valid Data
tCLZ tOEA
I/O1-I/O16 OH (Outputs) V
OL
V
Hi-Z
Hi-Z
"H" or "L"
Write Cycle (OE Controlled Write)
Semiconductor Group
19
HYB 3164(5)160T-50/-60 4M x 16-DRAM
tRWC tRAS
V IH VIL
tRP
RAS
tCSH tRCD tRSH tCAS tCRP
UCAS LCAS
V IH VIL
tRAH
V Address IH VIL
tCAH tASC
Column Address
tASR
Row Address
tASR
Row Address
tRAD
V IH
tAWD tCWD tRWD
tCWL tRWL tWP
WRITE
VIL
tAA tRCS
V IH
tOEA
tOEH
OE
VIL
tDZO tDZC
tDS tDH
Valid Data in
I/O1-I/O16 (Inputs) VIL
V IH
tCLZ tCAC
Data Out
tODD tOEZ
V I/O1-I/O16 OH
(Outputs) V OL
tRAC
"H" or "L"
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
20
tRASP tRP tPRWC tCP tCAS tCAS tCAH tASC tASC
Column Address Column Address
V
RAS
IH
V IL
tCSH tRSH tCAS tRAL tASR
Row Address
tRCD tCRP
Semiconductor Group
V
CAS
IH
V IL
tRAD tCAH tASC
Column Address
tASR
tRAH
tCAH
V
Address
IH
V IL
Row Address
Fast Page Mode Read-Modify-Write Cycle
V
tRCS tAA tOEA tOEA tWP tWP tOEA tAWD tAWD tAWD
tRWD tCWD tCWL tCWL
tCPWD tCWD
tCPWD tCWD
tRWL tCWL
WRITE
IH
21
V IL
tWP
V
IH
OE
V IL
tCPA tDZC
Data In
tCPA tODD
Data In
V
IH
tDZC tCLZ tDZO tCLZ tCAC tRAC tOEZ tDH tDS
Data Out Data Out
tDZC tCLZ tOEH
tODD
Data In
I/O1-I/O16 (Inputs) V IL
tODD tCAC tAA
tOEH tOEZ tDS tDH
tOEH tAA tDS
Data Out
tDH
I/O1-I/O16VOH (Outputs) V
OL
HYB 3164(5)160T-50/-60 4M x 16-DRAM
"H" or "L"
HYB 3164(5)160T-50/-60 4M x 16-DRAM
tRASP
V IH
tRP
RAS
VIL
tRCD
UCAS LCAS
V IH VIL
tPC tCP tCAS tCSH tCAS
tRHCP tRSH tCAS tCRP
tRAH tASR
Address
V IH VIL
Row Addr
tASC
tCAH
Column Address
tASC
tCAH tASC
tCAH tASR
Row Address Column Address
Column Address
tRAD tRCH tRCS tRCS tRCS
tRCH
V IH
WRITE
VIL
V IH
tAA tOEA
tCPA tAA tOEA
tCPA tAA tOEA tDZC tDZO tODD
tRRH
OE
VIL
tDZC tDZO tODD tCAC tOFF tCLZ tOFF tOEZ
Valid Data Out
tDZC tDZO
tCDD tODD
I/O1-I/O16 IH (Inputs) V
IL
V
tCAC tOFF tCLZ tOEZ
Valid Data Out
tCAC tCLZ
tOFF tOEZ
Valid Data Out
I/O1-I/O16 OH (Outputs) V
OL
V
"H" or "L"
Fast Page Mode Read Cycle
Semiconductor Group
22
HYB 3164(5)160T-50/-60 4M x 16-DRAM
tRASP
V IH
tRP
RAS
VIL
tPC tCAS tRCD tCP
tCAS
tRSH tCAS tCRP
UCAS LCAS
V IH VIL
tRAL tRAH tASR tCAH tASC
Column Address
tASC tCAH
Column Address
Address
V IH VIL
tASC
tCAH
tASR
Column Address
Row Addr
Column Address
tRAD
V IH VIL
tCWL tWCS tWCH tWP
tCWL tWCS tWCH tWP
tCWL tRWL tWCS tWCH tWP
WRITE
OE
V IH VIL
tDH tDS
V I/O1-I/O16 IH
tDH tDS
Valid Data In
tDH tDS
Valid Data In
(Inputs)
VIL
Valid Data In
I/O1-I/O16 OH (Outputs) V
OL
V
HI-Z
"H" or "L"
Fast Page Mode Early Write Cycle
Semiconductor Group
23
HYB 3164(5)160T-50/-60 4M x 16-DRAM
tRC tRAS
RAS
V IH VIL
tRP
tCRP tRPC
UCAS LCAS
V IH VIL
tRAH tASR
tASR
Row Address
Address
V IH VIL
Row Address
I/O1-I/O16 OH (Outputs) V
OL
V
HI-Z
"H" or "L"
RAS-Only Refresh Cycle
Semiconductor Group
24
HYB 3164(5)160T-50/-60 4M x 16-DRAM
tRC tRP
RAS
V IH VIL
tRAS
tRP
tRPC tCSR
UCAS LCAS
V IH VIL
tCRP tCHR tRPC
tCP tWRP tWRH
WRITE
V IH VIL
tOEZ
OE
V IH VIL
tCDD
I/O1-I/O16 IH (Inputs) V
IL V
tODD
I/O1-I/O16 OH (Outputs)VOL
V HI-Z
tOFF
"H" or "L"
CAS-Before-RAS Refresh Cycle
Semiconductor Group
25
HYB 3164(5)160T-50/-60 4M x 16-DRAM
tRC
V IH VIL
tRC tRP tRAS tRP
tRAS
RAS
tRCD
UCAS LCAS
V IH VIL
tRSH tCHR tCRP
tRAD tRAH tASR tASC tWRP tCAH tWRH tASR
Row Address
Address
V IH VIL
Row Addr
Column Address
tRCS
WRITE
V IH VIL
tRRH
tAA tOEA
OE
V IH VIL
tDZC tDZO
tCDD tODD
V I/O1-I/O16 IH
(Inputs)
VIL
tCAC tCLZ tRAC tOEZ
Valid Data Out
tOFF
I/O1-I/O16 OH (Outputs) V
OL
V
HI-Z
"H" or "L"
Hidden Refresh Cycle (Read)
Semiconductor Group
26
HYB 3164(5)160T-50/-60 4M x 16-DRAM
tRC tRP
RAS
V IH VIL
tRC tRAS tRP
tRAS
tRCD
UCAS LCAS
V IH VIL
tRSH
tCHR
tCRP
tRAD tRAH tASR tASC tCAH
Column Address
tASR
Row Address
Address
V IH VIL
Row Addr
tWCS
tWCH tWP
WRITE
V IH VIL
OE
V IH VIL
tDS
I/O1-I/O16 IH (Inputs) V
IL V
tDH
Valid Data
I/O1-I/O16 OH (Outputs) V
OL
V
HI-Z
"H" or "L"
Hidden Refresh Cycle (Early Write)
Semiconductor Group
27
HYB 3164(5)160T-50/-60 4M x 16-DRAM
V
tRAS
IH
tRP tRSH tCAS tRAL tASR
Row Address
RAS
V
IL
tCSR
V
tCHR
tCPT
CAS
IH
V
IL
V
tASC
IH
tCAH tAA
Address
V
IL
Column Address
Read Cycle
WRITE
V V IH
tWRP tWRH
IL
tRCS
tCAC
tRRH tRCH
tOEA
V
OE
V
IH
IL
I/O1-I/O16 (Inputs)
V V
tDZC tDZO
tODD tCLZ tOEZ
Valid Data Out
tCDD tOFF
IH
IL
I/O1-I/O16 (Outputs)
V OH V OL
Write Cycle
V IH
tWRP tWRH
tWCS
tWCH
tRWL tCWL
WRITE
V V
IL IH
OE
V
IL
tDS
I/O1-I/O16 (Inputs) I/O1-I/O16 (Outputs)
V V IH IL IH IL IH HI-Z
tDH
Valit Data In
V V
Read-Modify-Write Cycle
V
tWRP
tWRH
tRCS tAA
tAWD tCWD tCAC tOEA tDS
tCWL tRWL tWP tOEH
WRITE
V
IL
V
OE
IH
V
IL
I/O1-I/O16 (Inputs)
V V
tDZC tDZO
IH
tDH
Data In
IL
I/O1-I/O16 (Outputs)
V OH V OL HI-Z
tCLZ
tCAC
D.Out
tODD tOEZ
HI-Z
CAS-Before-RAS Refresh Counter Test Cycle
Semiconductor Group
28
HYB 3164(5)160T-50/-60 4M x 16-DRAM
tRP
RAS
V IH VIL
tRASS
tRPS
tRPC tCSR
UCAS LCAS
V IH VIL
tCHS
tCRP
tCP tWRP tWRH
WRITE
V IH VIL
tOEZ
OE
V IH VIL
tCDD
I/O1-I/O16 IH (Inputs) V IL
V
tODD
I/O1-I/O16 OH (Outputs) V OL
V HI-Z
tOFF
"H" or "L"
CAS-before-RAS Self Refresh
Semiconductor Group
29
HYB 3164(5)160T-50/-60 4M x 16-DRAM
Package Outlines
P-TSOPII-54-1 (500 mil) (Plastic Thin Small Outline Package Type II
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 30
Dimensions in mm

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